FIG. 8 is a cross-sectional view of a conventional GaAs semiconductor wafer before a dicing process. Semiconductor chips 1 are mechanically connected to each other by metal films 3 comprising gold or the like, so that the strength of the wafer comprising is increased. Each chip is about 40 to 50 microns thick and has an active element and a passive element on its main surface. The metal films 3 are formed by electroless plating. An Au layer 4 is disposed on the rear surface of the wafer through an intermediate feeding layer 14, so that heat is efficiently radiated from heat generating elements (not shown) on the semiconductor substrates. The Au layer 4 is generally called as a plated heat sink (hereafter referred to as PHS).
A method for producing the semiconductor wafer of FIG. 8 is illustrated in FIGS. 9(a)-9(e).
Initially, as illustrated in FIG. 9(a), a surface of the GaAs wafer 1 approximately 600 microns thick is partially etched away to form grooves 2 approximately 30 microns depth. The grooves 2 serve as dicing lines in a dicing process.
Then, as illustrated in FIG. 9(b), metal films 3 each having a thickness of 2 to 3 microns and comprising gold are formed in the grooves 2 by electroless plating. Thereafter, the GaAs wafer 1 is ground from the rear surface until the metal films 3 are exposed, resulting in a plurality of semiconductor chips 1 comprising the wafer and connected to each other by the metal films 3 as shown in FIG. 9(c).
Then, as illustrated in FIG. 9(d), a feeding layer 14 approximately several microns thick comprising gold or the like is formed over the rear surface of the wafer. Then, as illustrated in FIG. 9(e), a PHS layer 4 approximately 40 microns thick is formed on the feeding layer 14.
In the conventional method for producing semiconductor chips, before the formation of the PHS layer 4, the GaAs chips 1 are connected to each other by only the metal films 3, so that the strength of the whole wafer is poor in resisting stress applied in the production process, such as handling. Therefore, as illustrated in FIG. 10(a), the metal film 3 unfavorably rises (portion 10 in the figure) or sinks (portion 11 in the figure), whereby the wafer unfavorably curves i.e., becomes non-planar. Then, the feeding layer 14 and the plated heat sink 4 are formed on the rear surface of the curved wafer as illustrated in FIG. 10(b). When the wafer with the PHS layer 4 is cut by a blade 6 of a dicer (not shown) as illustrated in FIG. 10(c), if a depth of cut is adjusted to a line C at a point A, the blade 6 reaches only halfway in the PHS layer 4 at a point B due to the sinking portion 11, so that the dicing is not perfectly carried out. On the other hand, if the depth of cut is adjusted at the point B, a tape 5 applied to the PHS layer 4 is unfavorably cut at the point A, so that the dicing cannot be carried on, thereby reducing production yield.
In addition, since the metal film 3 and the PHS layer 4, both comprising a relatively soft metal like gold, are present beneath the dicing line 2, burrs 7 and 8 are produced after the dicing as illustrated in FIG. 11(a). When such a semiconductor chip is mounted on a package 17 and a wire 16 is connected to elements on the chip 1 as illustrated in FIG. 11(b), the wire 16 unfavorably contacts the burr 7, causing a short circuit. In addition, solder 18 is not evenly adhered to the PHS layer 4 because of the burr 8, so that the chip is not precisely die-bonded, causing a misassembly.
FIGS. 11(c) and 11(d) illustrate measuring characteristics of elements on the GaAs wafer 1. In FIG. 11(c), the semiconductor wafer of FIG. 10(b) is put on a stage 12 and air is evacuated through a hole 13 to fix the wafer onto the stage 12. However, because of the rising portion 10, the wafer cannot be fixed onto the stage 12. Even if the wafer is fixed to the stage 12 somehow, the GaAs wafer 1 inclines with respect to a horizontal plane D as illustrated in FIG. 11(d). In this case, an RF probe terminal 9 does not properly contact the elements on the chip 1, resulting in an inaccurate measurement.
Meanwhile, a method for dividing a semiconductor wafer into a plurality of chips by etching, a so-called pellet separation method, is employed in, for example, Japanese Published Patent Applications Nos. 62-122279, 2-148739, and 2-214127. In this method, although no burrs are produced, it is difficult to control the dimensions of each chip after the separation. In addition, because the chips after the etching process, are separated from each other, a rapid transition to the subsequent die-bonding process is prevented. This results in a poor production yield. In addition, it is not possible to selectively pick out non-defective chips which are tested before the separation. Therefore, this method is not suitable for processing and testing.